Among current ADC structures, a flash ADC and a time-interleaved ADC have highest operating speeds. For high-speed applications, an area and power consumption of the flash ADC are exponentially enlarged as a sampling rate and a resolution increase, whereas the time-interleave ADC satisfies the high-speed applications better than the flash ADC. However, the time-interleaved ADC directly and severely reduces a signal-to-noise ratio (SNR) in the event of timing mismatch, and the SNR degradation worsens even more drastically as the operating speed gets higher. Therefore, there is a need for a solution for increasing the SNR in the event of timing mismatch for the time-interleaved ADC.